Shoumei RV64G CPU — Instruction Performance Benchmarks

⚠ Architectural Caveats & Performance Notes

Microcoded Zb* Bitmanip Instructions: Un-decoded Zb* bitmanip operations (sh1add, bset, bclr, binv, clmul, min, max, rol, ror, etc.) are emulated via microcode fallback in FallbackSequencer. Each fallback instruction completely drains and serializes the pipeline, flushes stale fetches, and executes sequentially (~0.170 IPC — these are microcoded and thus suck 😉). Dedicated single-cycle hardware execution units are planned for future revisions.
Atomic Memory Operations (AMO): All AMOs serialize at the Store Buffer and memory hierarchy boundary to guarantee sequential consistency.
CSR Instructions: Control and status register instructions (csrrw, csrrs, etc.) serialize the pipeline and execute via CSRFile, bypassing the standard ROB integer retirement path (and do not increment minstret in hardware).

Instruction	Extension	Peak IPC (Throughput)	Dependent IPC (Latency)	Pipeline Unit / Execution Path
add	RV64I (Base)	1.933	1.237	ALU0 / ALU1
add_uw	RV64I (Word)	0.093	—	ALU0 / ALU1
addi	RV64I (Base)	1.933	1.237	ALU0 / ALU1
addiw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
addw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
amoadd_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoadd_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoand_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoand_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amomax_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amomax_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amomaxu_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amomaxu_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amomin_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amomin_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amominu_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amominu_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoor_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoor_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoswap_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoswap_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoxor_d	RV64A	0.257	—	LSU / StoreBuffer (atomic)
amoxor_w	RV64A	0.257	—	LSU / StoreBuffer (atomic)
and	RV64I (Base)	1.933	1.237	ALU0 / ALU1
andi	RV64I (Base)	1.933	1.237	ALU0 / ALU1
andn	Zbb	0.102	—	FallbackSequencer (microcode)
auipc	RV64I (Base)	1.776	—	ALU0 / ALU1
bclr	Zbs	0.102	—	FallbackSequencer (microcode)
bclri	RV64I (Base)	0.102	—	ALU0 / ALU1
beq	RV64I (Control)	1.013	0.372	BranchExecUnit
bext	Zbs	0.102	—	FallbackSequencer (microcode)
bexti	RV64I (Base)	0.102	—	ALU0 / ALU1
bge	RV64I (Control)	1.013	0.372	BranchExecUnit
bgeu	RV64I (Control)	1.013	0.372	BranchExecUnit
binv	Zbs	0.102	—	FallbackSequencer (microcode)
binvi	RV64I (Base)	0.102	—	ALU0 / ALU1
blt	RV64I (Control)	1.013	0.372	BranchExecUnit
bltu	RV64I (Control)	1.013	0.372	BranchExecUnit
bne	RV64I (Control)	1.013	0.372	BranchExecUnit
bset	Zbs	0.102	—	FallbackSequencer (microcode)
bseti	RV64I (Base)	0.102	—	ALU0 / ALU1
clmul	Zbc	0.102	—	FallbackSequencer (microcode)
clmulh	RV64I (Base)	0.102	—	ALU0 / ALU1
clmulr	RV64I (Base)	0.102	—	ALU0 / ALU1
clz	RV64I (Base)	0.113	—	ALU0 / ALU1
clzw	RV64I (Word)	0.085	—	ALU0 / ALU1
cpop	RV64I (Base)	0.113	—	ALU0 / ALU1
cpopw	RV64I (Word)	0.102	—	ALU0 / ALU1
csrrc	Zicsr	0.006	0.046	CSRFile (serialized)
csrrci	Zicsr	0.006	—	CSRFile (serialized)
csrrs	Zicsr	0.006	0.046	CSRFile (serialized)
csrrsi	Zicsr	0.006	—	CSRFile (serialized)
csrrw	Zicsr	0.006	0.046	CSRFile (serialized)
csrrwi	Zicsr	0.006	—	CSRFile (serialized)
ctz	RV64I (Base)	0.113	—	ALU0 / ALU1
ctzw	RV64I (Word)	0.113	—	ALU0 / ALU1
div	RV64M	0.015	0.019	Divider (iterative SRT)
divu	RV64M	0.015	0.019	Divider (iterative SRT)
divuw	RV64M	0.015	0.019	Divider (iterative SRT)
divw	RV64M	0.015	0.019	Divider (iterative SRT)
fadd_d	RV64D	1.012	0.311	FPExecUnit (pipelined)
fadd_s	RV64F	1.012	0.311	FPExecUnit (pipelined)
fclass_d	RV64D	1.012	—	FPExecUnit (pipelined)
fclass_s	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_d_l	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_d_lu	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_d_s	RV64F	1.013	0.622	FPExecUnit (pipelined)
fcvt_d_w	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_d_wu	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_l_d	RV64D	1.012	—	FPExecUnit (pipelined)
fcvt_l_s	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_lu_d	RV64D	1.012	—	FPExecUnit (pipelined)
fcvt_lu_s	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_s_d	RV64D	1.013	0.622	FPExecUnit (pipelined)
fcvt_s_l	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_s_lu	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_s_w	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_s_wu	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_w_d	RV64D	1.012	—	FPExecUnit (pipelined)
fcvt_w_s	RV64F	1.012	—	FPExecUnit (pipelined)
fcvt_wu_d	RV64D	1.012	—	FPExecUnit (pipelined)
fcvt_wu_s	RV64F	1.012	—	FPExecUnit (pipelined)
fdiv_d	RV64D	0.018	0.022	FPU Divider / Sqrt
fdiv_s	RV64F	0.040	0.049	FPU Divider / Sqrt
fence	Zifencei	1.991	—	Pipeline drain / flush
feq_d	RV64D	1.012	—	FPExecUnit (pipelined)
feq_s	RV64F	1.012	—	FPExecUnit (pipelined)
fld	RV64F	0.515	—	FPExecUnit (pipelined)
fle_d	RV64D	1.012	—	FPExecUnit (pipelined)
fle_s	RV64F	1.012	—	FPExecUnit (pipelined)
flt_d	RV64D	1.012	—	FPExecUnit (pipelined)
flt_s	RV64F	1.012	—	FPExecUnit (pipelined)
flw	RV64F	0.515	—	FPExecUnit (pipelined)
fmadd_d	RV64D	1.012	0.156	FPExecUnit (pipelined)
fmadd_s	RV64F	1.012	0.208	FPExecUnit (pipelined)
fmax_d	RV64D	1.013	0.622	FPExecUnit (pipelined)
fmax_s	RV64F	1.013	0.622	FPExecUnit (pipelined)
fmin_d	RV64D	1.013	0.622	FPExecUnit (pipelined)
fmin_s	RV64F	1.013	0.622	FPExecUnit (pipelined)
fmsub_d	RV64D	1.012	0.156	FPExecUnit (pipelined)
fmsub_s	RV64F	1.012	0.208	FPExecUnit (pipelined)
fmul_d	RV64D	1.012	0.311	FPExecUnit (pipelined)
fmul_s	RV64F	1.012	0.415	FPExecUnit (pipelined)
fmv_d_x	RV64F	1.012	—	FPExecUnit (pipelined)
fmv_w_x	RV64F	1.012	—	FPExecUnit (pipelined)
fmv_x_d	RV64D	1.012	—	FPExecUnit (pipelined)
fmv_x_w	RV64F	1.012	—	FPExecUnit (pipelined)
fnmadd_d	RV64D	1.012	0.156	FPExecUnit (pipelined)
fnmadd_s	RV64F	1.012	0.208	FPExecUnit (pipelined)
fnmsub_d	RV64D	1.012	0.156	FPExecUnit (pipelined)
fnmsub_s	RV64F	1.012	0.208	FPExecUnit (pipelined)
fsd	RV64F	1.012	—	FPExecUnit (pipelined)
fsgnj_d	RV64D	1.013	0.622	FPExecUnit (pipelined)
fsgnj_s	RV64F	1.013	0.622	FPExecUnit (pipelined)
fsgnjn_d	RV64D	1.013	0.622	FPExecUnit (pipelined)
fsgnjn_s	RV64F	1.013	0.622	FPExecUnit (pipelined)
fsgnjx_d	RV64D	1.013	0.622	FPExecUnit (pipelined)
fsgnjx_s	RV64F	1.013	0.622	FPExecUnit (pipelined)
fsqrt_d	RV64D	0.018	0.022	FPU Divider / Sqrt
fsqrt_s	RV64F	0.040	0.049	FPU Divider / Sqrt
fsub_d	RV64D	1.012	0.311	FPExecUnit (pipelined)
fsub_s	RV64F	1.012	0.311	FPExecUnit (pipelined)
fsw	RV64F	1.012	—	FPExecUnit (pipelined)
jal	RV64I (Control)	0.170	—	BranchExecUnit
jalr	RV64I (Control)	0.378	—	BranchExecUnit
lb	RV64I (Load/Store)	0.515	0.415	LSU / L1D Cache
lbu	RV64I (Load/Store)	0.515	0.415	LSU / L1D Cache
ld	RV64I (Load/Store)	0.515	0.415	LSU / L1D Cache
lh	RV64I (Load/Store)	0.515	0.415	LSU / L1D Cache
lhu	RV64I (Load/Store)	0.515	0.415	LSU / L1D Cache
lr_d	RV64A	0.343	—	LSU / StoreBuffer (atomic)
lr_w	RV64A	0.343	—	LSU / StoreBuffer (atomic)
lui	RV64I (Base)	1.776	—	ALU0 / ALU1
lw	RV64I (Word)	0.515	0.415	ALU0 / ALU1
lwu	RV64I (Load/Store)	0.515	0.415	LSU / L1D Cache
max	Zbb	0.102	—	FallbackSequencer (microcode)
maxu	Zbb	0.102	—	FallbackSequencer (microcode)
min	Zbb	0.102	—	FallbackSequencer (microcode)
minu	Zbb	0.102	—	FallbackSequencer (microcode)
mul	RV64M	1.013	0.415	Multiplier (pipelined)
mulh	RV64M	1.013	0.415	Multiplier (pipelined)
mulhsu	RV64M	1.013	0.415	Multiplier (pipelined)
mulhu	RV64M	1.013	0.415	Multiplier (pipelined)
mulw	RV64M	1.013	0.415	Multiplier (pipelined)
or	RV64I (Base)	1.933	1.237	ALU0 / ALU1
orc_b	RV64I (Base)	0.113	—	ALU0 / ALU1
ori	RV64I (Base)	1.933	1.237	ALU0 / ALU1
orn	Zbb	0.102	—	FallbackSequencer (microcode)
rem	RV64M	0.015	0.019	Divider (iterative SRT)
remu	RV64M	0.015	0.019	Divider (iterative SRT)
remuw	RV64M	0.015	0.019	Divider (iterative SRT)
remw	RV64M	0.015	0.019	Divider (iterative SRT)
rev8	RV64I (Base)	0.113	—	ALU0 / ALU1
rol	Zbb	0.102	—	FallbackSequencer (microcode)
rolw	RV64I (Word)	0.102	—	ALU0 / ALU1
ror	Zbb	0.102	—	FallbackSequencer (microcode)
rori	RV64I (Base)	0.102	—	ALU0 / ALU1
roriw	RV64I (Word)	0.102	—	ALU0 / ALU1
rorw	RV64I (Word)	0.102	—	ALU0 / ALU1
sb	RV64I (Load/Store)	1.012	—	LSU / L1D Cache
sc_d	RV64A	0.515	—	LSU / StoreBuffer (atomic)
sc_w	RV64A	0.515	—	LSU / StoreBuffer (atomic)
sd	RV64I (Load/Store)	1.012	—	LSU / L1D Cache
sext_b	RV64I (Base)	0.093	—	ALU0 / ALU1
sext_h	RV64I (Base)	0.093	—	ALU0 / ALU1
sh	RV64I (Load/Store)	1.012	—	LSU / L1D Cache
sh1add	Zba	0.102	—	FallbackSequencer (microcode)
sh1add_uw	RV64I (Word)	0.093	—	ALU0 / ALU1
sh2add	Zba	0.102	—	FallbackSequencer (microcode)
sh2add_uw	RV64I (Word)	0.093	—	ALU0 / ALU1
sh3add	Zba	0.102	—	FallbackSequencer (microcode)
sh3add_uw	RV64I (Word)	0.093	—	ALU0 / ALU1
sll	RV64I (Base)	1.933	1.237	ALU0 / ALU1
slli	RV64I (Base)	1.933	1.237	ALU0 / ALU1
slli_uw	RV64I (Word)	0.093	—	ALU0 / ALU1
slliw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
sllw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
slt	RV64I (Base)	1.933	1.237	ALU0 / ALU1
slti	RV64I (Base)	1.933	1.237	ALU0 / ALU1
sltiu	RV64I (Base)	1.933	1.237	ALU0 / ALU1
sltu	RV64I (Base)	1.933	1.237	ALU0 / ALU1
sra	RV64I (Base)	1.933	1.237	ALU0 / ALU1
srai	RV64I (Base)	1.933	1.237	ALU0 / ALU1
sraiw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
sraw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
srl	RV64I (Base)	1.933	1.237	ALU0 / ALU1
srli	RV64I (Base)	1.933	1.237	ALU0 / ALU1
srliw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
srlw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
sub	RV64I (Base)	1.933	1.237	ALU0 / ALU1
subw	RV64I (Word)	1.933	1.237	ALU0 / ALU1
sw	RV64I (Word)	1.012	—	ALU0 / ALU1
xnor	Zbb	0.102	—	FallbackSequencer (microcode)
xor	RV64I (Base)	1.933	1.237	ALU0 / ALU1
xori	RV64I (Base)	1.933	1.237	ALU0 / ALU1
zext_h	RV64I (Base)	0.093	—	ALU0 / ALU1

Instruction

Extension

Peak IPC (Throughput)

Dependent IPC (Latency)

Pipeline Unit / Execution Path

add

RV64I (Base)

1.933

1.237

ALU0 / ALU1

add_uw

RV64I (Word)

0.093

—

ALU0 / ALU1

addi

RV64I (Base)

1.933

1.237

ALU0 / ALU1

addiw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

addw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

amoadd_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoadd_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoand_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoand_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amomax_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amomax_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amomaxu_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amomaxu_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amomin_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amomin_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amominu_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amominu_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoor_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoor_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoswap_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoswap_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoxor_d

RV64A

0.257

—

LSU / StoreBuffer (atomic)

amoxor_w

RV64A

0.257

—

LSU / StoreBuffer (atomic)

and

RV64I (Base)

1.933

1.237

ALU0 / ALU1

andi

RV64I (Base)

1.933

1.237

ALU0 / ALU1

andn

Zbb

0.102

—

FallbackSequencer (microcode)

auipc

RV64I (Base)

1.776

—

ALU0 / ALU1

bclr

Zbs

0.102

—

FallbackSequencer (microcode)

bclri

RV64I (Base)

0.102

—

ALU0 / ALU1

beq

RV64I (Control)

1.013

0.372

BranchExecUnit

bext

Zbs

0.102

—

FallbackSequencer (microcode)

bexti

RV64I (Base)

0.102

—

ALU0 / ALU1

bge

RV64I (Control)

1.013

0.372

BranchExecUnit

bgeu

RV64I (Control)

1.013

0.372

BranchExecUnit

binv

Zbs

0.102

—

FallbackSequencer (microcode)

binvi

RV64I (Base)

0.102

—

ALU0 / ALU1

blt

RV64I (Control)

1.013

0.372

BranchExecUnit

bltu

RV64I (Control)

1.013

0.372

BranchExecUnit

bne

RV64I (Control)

1.013

0.372

BranchExecUnit

bset

Zbs

0.102

—

FallbackSequencer (microcode)

bseti

RV64I (Base)

0.102

—

ALU0 / ALU1

clmul

Zbc

0.102

—

FallbackSequencer (microcode)

clmulh

RV64I (Base)

0.102

—

ALU0 / ALU1

clmulr

RV64I (Base)

0.102

—

ALU0 / ALU1

clz

RV64I (Base)

0.113

—

ALU0 / ALU1

clzw

RV64I (Word)

0.085

—

ALU0 / ALU1

cpop

RV64I (Base)

0.113

—

ALU0 / ALU1

cpopw

RV64I (Word)

0.102

—

ALU0 / ALU1

csrrc

Zicsr

0.006

0.046

CSRFile (serialized)

csrrci

Zicsr

0.006

—

CSRFile (serialized)

csrrs

Zicsr

0.006

0.046

CSRFile (serialized)

csrrsi

Zicsr

0.006

—

CSRFile (serialized)

csrrw

Zicsr

0.006

0.046

CSRFile (serialized)

csrrwi

Zicsr

0.006

—

CSRFile (serialized)

ctz

RV64I (Base)

0.113

—

ALU0 / ALU1

ctzw

RV64I (Word)

0.113

—

ALU0 / ALU1

div

RV64M

0.015

0.019

Divider (iterative SRT)

divu

RV64M

0.015

0.019

Divider (iterative SRT)

divuw

RV64M

0.015

0.019

Divider (iterative SRT)

divw

RV64M

0.015

0.019

Divider (iterative SRT)

fadd_d

RV64D

1.012

0.311

FPExecUnit (pipelined)

fadd_s

RV64F

1.012

0.311

FPExecUnit (pipelined)

fclass_d

RV64D

1.012

—

FPExecUnit (pipelined)

fclass_s

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_d_l

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_d_lu

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_d_s

RV64F

1.013

0.622

FPExecUnit (pipelined)

fcvt_d_w

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_d_wu

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_l_d

RV64D

1.012

—

FPExecUnit (pipelined)

fcvt_l_s

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_lu_d

RV64D

1.012

—

FPExecUnit (pipelined)

fcvt_lu_s

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_s_d

RV64D

1.013

0.622

FPExecUnit (pipelined)

fcvt_s_l

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_s_lu

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_s_w

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_s_wu

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_w_d

RV64D

1.012

—

FPExecUnit (pipelined)

fcvt_w_s

RV64F

1.012

—

FPExecUnit (pipelined)

fcvt_wu_d

RV64D

1.012

—

FPExecUnit (pipelined)

fcvt_wu_s

RV64F

1.012

—

FPExecUnit (pipelined)

fdiv_d

RV64D

0.018

0.022

FPU Divider / Sqrt

fdiv_s

RV64F

0.040

0.049

FPU Divider / Sqrt

fence

Zifencei

1.991

—

Pipeline drain / flush

feq_d

RV64D

1.012

—

FPExecUnit (pipelined)

feq_s

RV64F

1.012

—

FPExecUnit (pipelined)

fld

RV64F

0.515

—

FPExecUnit (pipelined)

fle_d

RV64D

1.012

—

FPExecUnit (pipelined)

fle_s

RV64F

1.012

—

FPExecUnit (pipelined)

flt_d

RV64D

1.012

—

FPExecUnit (pipelined)

flt_s

RV64F

1.012

—

FPExecUnit (pipelined)

flw

RV64F

0.515

—

FPExecUnit (pipelined)

fmadd_d

RV64D

1.012

0.156

FPExecUnit (pipelined)

fmadd_s

RV64F

1.012

0.208

FPExecUnit (pipelined)

fmax_d

RV64D

1.013

0.622

FPExecUnit (pipelined)

fmax_s

RV64F

1.013

0.622

FPExecUnit (pipelined)

fmin_d

RV64D

1.013

0.622

FPExecUnit (pipelined)

fmin_s

RV64F

1.013

0.622

FPExecUnit (pipelined)

fmsub_d

RV64D

1.012

0.156

FPExecUnit (pipelined)

fmsub_s

RV64F

1.012

0.208

FPExecUnit (pipelined)

fmul_d

RV64D

1.012

0.311

FPExecUnit (pipelined)

fmul_s

RV64F

1.012

0.415

FPExecUnit (pipelined)

fmv_d_x

RV64F

1.012

—

FPExecUnit (pipelined)

fmv_w_x

RV64F

1.012

—

FPExecUnit (pipelined)

fmv_x_d

RV64D

1.012

—

FPExecUnit (pipelined)

fmv_x_w

RV64F

1.012

—

FPExecUnit (pipelined)

fnmadd_d

RV64D

1.012

0.156

FPExecUnit (pipelined)

fnmadd_s

RV64F

1.012

0.208

FPExecUnit (pipelined)

fnmsub_d

RV64D

1.012

0.156

FPExecUnit (pipelined)

fnmsub_s

RV64F

1.012

0.208

FPExecUnit (pipelined)

fsd

RV64F

1.012

—

FPExecUnit (pipelined)

fsgnj_d

RV64D

1.013

0.622

FPExecUnit (pipelined)

fsgnj_s

RV64F

1.013

0.622

FPExecUnit (pipelined)

fsgnjn_d

RV64D

1.013

0.622

FPExecUnit (pipelined)

fsgnjn_s

RV64F

1.013

0.622

FPExecUnit (pipelined)

fsgnjx_d

RV64D

1.013

0.622

FPExecUnit (pipelined)

fsgnjx_s

RV64F

1.013

0.622

FPExecUnit (pipelined)

fsqrt_d

RV64D

0.018

0.022

FPU Divider / Sqrt

fsqrt_s

RV64F

0.040

0.049

FPU Divider / Sqrt

fsub_d

RV64D

1.012

0.311

FPExecUnit (pipelined)

fsub_s

RV64F

1.012

0.311

FPExecUnit (pipelined)

fsw

RV64F

1.012

—

FPExecUnit (pipelined)

jal

RV64I (Control)

0.170

—

BranchExecUnit

jalr

RV64I (Control)

0.378

—

BranchExecUnit

RV64I (Load/Store)

0.515

0.415

LSU / L1D Cache

lbu

RV64I (Load/Store)

0.515

0.415

LSU / L1D Cache

RV64I (Load/Store)

0.515

0.415

LSU / L1D Cache

RV64I (Load/Store)

0.515

0.415

LSU / L1D Cache

lhu

RV64I (Load/Store)

0.515

0.415

LSU / L1D Cache

lr_d

RV64A

0.343

—

LSU / StoreBuffer (atomic)

lr_w

RV64A

0.343

—

LSU / StoreBuffer (atomic)

lui

RV64I (Base)

1.776

—

ALU0 / ALU1

RV64I (Word)

0.515

0.415

ALU0 / ALU1

lwu

RV64I (Load/Store)

0.515

0.415

LSU / L1D Cache

max

Zbb

0.102

—

FallbackSequencer (microcode)

maxu

Zbb

0.102

—

FallbackSequencer (microcode)

min

Zbb

0.102

—

FallbackSequencer (microcode)

minu

Zbb

0.102

—

FallbackSequencer (microcode)

mul

RV64M

1.013

0.415

Multiplier (pipelined)

mulh

RV64M

1.013

0.415

Multiplier (pipelined)

mulhsu

RV64M

1.013

0.415

Multiplier (pipelined)

mulhu

RV64M

1.013

0.415

Multiplier (pipelined)

mulw

RV64M

1.013

0.415

Multiplier (pipelined)

RV64I (Base)

1.933

1.237

ALU0 / ALU1

orc_b

RV64I (Base)

0.113

—

ALU0 / ALU1

ori

RV64I (Base)

1.933

1.237

ALU0 / ALU1

orn

Zbb

0.102

—

FallbackSequencer (microcode)

rem

RV64M

0.015

0.019

Divider (iterative SRT)

remu

RV64M

0.015

0.019

Divider (iterative SRT)

remuw

RV64M

0.015

0.019

Divider (iterative SRT)

remw

RV64M

0.015

0.019

Divider (iterative SRT)

rev8

RV64I (Base)

0.113

—

ALU0 / ALU1

rol

Zbb

0.102

—

FallbackSequencer (microcode)

rolw

RV64I (Word)

0.102

—

ALU0 / ALU1

ror

Zbb

0.102

—

FallbackSequencer (microcode)

rori

RV64I (Base)

0.102

—

ALU0 / ALU1

roriw

RV64I (Word)

0.102

—

ALU0 / ALU1

rorw

RV64I (Word)

0.102

—

ALU0 / ALU1

RV64I (Load/Store)

1.012

—

LSU / L1D Cache

sc_d

RV64A

0.515

—

LSU / StoreBuffer (atomic)

sc_w

RV64A

0.515

—

LSU / StoreBuffer (atomic)

RV64I (Load/Store)

1.012

—

LSU / L1D Cache

sext_b

RV64I (Base)

0.093

—

ALU0 / ALU1

sext_h

RV64I (Base)

0.093

—

ALU0 / ALU1

RV64I (Load/Store)

1.012

—

LSU / L1D Cache

sh1add

Zba

0.102

—

FallbackSequencer (microcode)

sh1add_uw

RV64I (Word)

0.093

—

ALU0 / ALU1

sh2add

Zba

0.102

—

FallbackSequencer (microcode)

sh2add_uw

RV64I (Word)

0.093

—

ALU0 / ALU1

sh3add

Zba

0.102

—

FallbackSequencer (microcode)

sh3add_uw

RV64I (Word)

0.093

—

ALU0 / ALU1

sll

RV64I (Base)

1.933

1.237

ALU0 / ALU1

slli

RV64I (Base)

1.933

1.237

ALU0 / ALU1

slli_uw

RV64I (Word)

0.093

—

ALU0 / ALU1

slliw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

sllw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

slt

RV64I (Base)

1.933

1.237

ALU0 / ALU1

slti

RV64I (Base)

1.933

1.237

ALU0 / ALU1

sltiu

RV64I (Base)

1.933

1.237

ALU0 / ALU1

sltu

RV64I (Base)

1.933

1.237

ALU0 / ALU1

sra

RV64I (Base)

1.933

1.237

ALU0 / ALU1

srai

RV64I (Base)

1.933

1.237

ALU0 / ALU1

sraiw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

sraw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

srl

RV64I (Base)

1.933

1.237

ALU0 / ALU1

srli

RV64I (Base)

1.933

1.237

ALU0 / ALU1

srliw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

srlw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

sub

RV64I (Base)

1.933

1.237

ALU0 / ALU1

subw

RV64I (Word)

1.933

1.237

ALU0 / ALU1

RV64I (Word)

1.012

—

ALU0 / ALU1

xnor

Zbb

0.102

—

FallbackSequencer (microcode)

xor

RV64I (Base)

1.933

1.237

ALU0 / ALU1

xori

RV64I (Base)

1.933

1.237

ALU0 / ALU1

zext_h

RV64I (Base)

0.093

—

ALU0 / ALU1

Shoumei RV64G CPU — Instruction Performance & Benchmark Suite

⚠ Architectural Caveats & Performance Notes