証明 Shoumei RTL — Architecture Visualizations AYAYA Vector SVG

Emitted natively by Lean 4 code generators • Byte-identical on every machine • Zero raster drift

Detailed CPU Gate Treemap (Lean RTL)

RV64G OoO CPU — Subsystems & Leaf Units

Deterministic vector SVG · Scalable to any resolution · Byte-identical on every host
RV64G OoO CPU — Subsystems & Leaf Units Treemap
Treemap SVG · 3D Gate City · 3D Hierarchy

Shoumei System-on-Chip (SoC) Interactive Architecture

Shoumei SoC — Top-Level Die, Interconnect & Peripherals

Interactive SVG block diagram: RV64G OoO CPU, TileLink TL-UH crossbar, ACLINT, APLIC, UART, GPIO, BootROM & SRAM

Launch Interactive SoC Diagram →   Includes pad ring pinout, TileLink bus flow & block inspector

Instruction Performance & Benchmarks (CPI / Latency)

RV64G + Zb* Instruction Performance — Cycle-Accurate Measurements

Measured cycle-accurate throughput and latency across all 171 instructions on Shoumei RTL

View Instruction Benchmark Results →   Interactive table with search, extension filters & pipeline metrics

Architectural Caveats:
• Microcoded Zb* bitmanip (sh1add, bset, clmul, etc.): Emulated via microcode fallback (FallbackSequencer), serializing the pipeline (~5.9 CPI). Dedicated single-cycle execution units planned for future revisions.
• Atomic memory operations (AMO): Serialized through the Store Buffer and memory hierarchy boundary.
• CSR instructions: Pipeline-serialized; execute via CSRFile and do not increment minstret in hardware.

Lean RTL Hierarchical Model

RV64G OoO CPU — Lean RTL (Subsystem Groups)

588,258 gates total · Vector SVG · Click figure for full size
RV64G OoO CPU — Lean RTL (Subsystem Groups) Treemap RV64G OoO CPU — Lean RTL (Subsystem Groups) Sunburst
Treemap SVG · Sunburst SVG · 3D Gate City · 3D Hierarchy

Lean Flat Netlist Model

Lean Flat Netlist (Per-Module Gate Counts)

520,465 gates across 230 modules
Lean Flat Netlist (Per-Module Gate Counts) Treemap Lean Flat Netlist (Per-Module Gate Counts) Sunburst
Treemap SVG · Sunburst SVG · 3D Gate City · 3D Hierarchy

GF180MCU Synthesis Netlist Model

GF180MCU Netlist (Yosys)

130,200 cells total · Vector SVG · Click figure for full size
GF180MCU Netlist (Yosys) Treemap GF180MCU Netlist (Yosys) Sunburst
Treemap SVG · Sunburst SVG · 3D Gate City · 3D Hierarchy

ASAP7 Synthesis Netlist Model

ASAP7 Netlist (Yosys)

168,731 cells total · Vector SVG · Click figure for full size
ASAP7 Netlist (Yosys) Treemap ASAP7 Netlist (Yosys) Sunburst
Treemap SVG · Sunburst SVG · 3D Gate City · 3D Hierarchy