Shoumei_SoC
Complete System-on-Chip Top
ASAP7 Cell Area
32,785 µm²
Block Description
Select any block or pad in the SoC diagram to inspect its interface, TileLink port assignment, register mappings, and verification proofs.
Key Ports & Interfaces
- clock INPUT (1b)
- reset_n INPUT (1b)
- uart_rx INPUT (1b)
- uart_tx OUTPUT (1b)
- gpio_i[7:0] INPUT (8b)
- gpio_o[7:0] OUTPUT (8b)
- mem_req_valid OUTPUT (1b)
- mem_resp_valid INPUT (1b)
Formal Verification & Provenance
Lean 4 DSL: lean/Shoumei/SoC/ShoumeiSoC.lean
Proofs: ShoumeiSoCProofs.lean (5 structural theorems, 100% discharge)
Certificate: shoumeiSoC_cert (9 compositional dependencies verified)